TMS320LF2403APAGA

digital signal processor controller, QFP-64, -0.3 V to 4.6 V, SCI/SPI Bootloader, Watchdog Timer Module

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Price:: US $7.00~12.00 / piece [Get Latest Price]

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PartNumber:: TMS320LF2403APAGA

Brand:: Texas Instruments - TI | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-07-07

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Part Number:TMS320LF2403APAGA
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Product Summary

The TMS320LF2403APAGA is a digital signal processor (DSP) controller. The device offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the TMS320LF2403APAGA offers increased processing performance (40 MIPS) and a higher level of peripheral integration.

Parametrics

TMS320LF2403APAGA absolute maximum ratings: (1)Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA: -0.3 V to 4.6 V; (2)VCCP range: -0.3 V to 5.5 V; (3)Input voltage range, VIN: -0.3 V to 4.6 V; (4)Output voltage range, VO: -0.3 V to 4.6 V; (5)Input clamp current, IIK (VIN < 0 or VIN > VCC): ±20 mA; (6)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (7)Operating free-air temperature ranges, TA: A version: -40℃ to 85℃; S version: -40℃ to 125℃; (8)Junction temperature range, TJ: -40℃ to 150℃; (9)Storage temperature range, Tstg: -65℃ to 150℃.

Features

TMS320LF2403APAGA features: (1)Controller Area Network (CAN) 2.0B Module; (2)Serial Communications Interface (SCI); (3)16-Bit Serial Peripheral Interface (SPI); (4)Phase-Locked-Loop (PLL)-Based Clock Generation; (5)Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins; (6)Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts); (7)Power Management: Three Power-Down Modes; Ability to Power Down Each Peripheral Independently; (8)Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1+(JTAG).