ENC424J600-I/PT

Product Summary

The ENC424J600-I/PT is a stand-alone, Fast Ethernet controller with an industry standard Serial Peripheral Interface (SPI) or a flexible parallel interface. The ENC424J600-I/PT is designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port. The ENC424J600-I/PT meets all of the IEEE 802.3 specifications applicable to 10Base-T and 100Base-TX Ethernet, including many optional clauses, such as auto-negotiation. The ENC424J600-I/PT incorporates a number of packet filtering schemes to limit incoming packets. The device also provides an internal, 16-bit wide DMA for fast data throughput and support for hardware IP checksum calculations.

Parametrics

ENC424J600-I/PT absolute maximum ratings: (1)Storage temperature: -65℃ to +150℃; (2)Ambient temperature under bias: -40℃ to +85℃ (Industrial); (3)Voltage on VDD, VDDOSC, VDDPLL, VDDRX and VDDTX, with respect to VSS: -0.3V to 4.0V; (4)Voltage on any digital pin, with respect to VSS: -0.3V to 6.0V; (5)Voltage on OSC1 and RBIAS analog pins, with respect to VSS: -0.3V to VDD + 0.3V; (6)Voltage on TPIN+/- and TPOUT+/-, with respect to VSS: -0.3V to 5.0V; (7)Voltage on VCAP, with respect to all VSS pins (Note 1): -0.3V to 2.0V; (8)ESD protection on all pins: 2 kV; (9)Current sourced or sunk by any digital output pin: 25 mA; (10)Current out of all VSS pins: 420 mA; (11)Current into all VDD pins: 300 mA.

Features

ENC424J600-I/PT features: (1)IEEE 802.3 Compliant Fast Ethernet Controller; (2)Integrated MAC and 10/100Base-T PHY; (3)Hardware Security Acceleration Engines; (4)24-Kbyte Transmit/Receive Packet Buffer SRAM; (5)Supports one 10/100Base-T Port with Automatic Polarity Detection and Correction; (6)Supports Auto-Negotiation; (7)Support for Pause Control Frames, including Automatic Transmit and Receive Flow Control; (8)Supports Half and Full-Duplex Operation; (9)Programmable Automatic Retransmit on Collision; (10)Programmable Padding and CRC Generation; (11)Programmable Automatic Rejection of Erroneous and Runt Packets; (12)Factory Preprogrammed Unique MAC Address.

Diagrams